In charged-particle-beam (CPB) projection-microlithography as used in the fabrication of integrated circuits, a circuit pattern defined by a reticle or mask is irradiated with a charged-particle beam to transfer the pattern defined by the reticle or mask to a sensitized substrate (e.g., a semiconductor wafer). In recent years, CPB projection-microlithography apparatus ("pattern-transfer apparatus") have been developed that exhibit improved resolution of the transferred pattern and improved product throughput (i.e., the number of semiconductor wafers that can be exposed with a pattern per unit time). With certain conventional CPB pattern-transfer apparatus, one or more entire die patterns defined on a mask are transferred onto the wafer in a single exposure. A "die" is a pattern coextensive with the bounds of an integrated circuit or other device to be transferred onto the wafer (usually multiple dies are exposed at respective locations on the wafer).
It is difficult to produce a mask for a CPB pattern-transfer apparatus that transfers multiple dies or even an entire die in a single exposure while also providing the high resolution and circuit densities demanded in recent years. In addition, conventional CPB pattern-transfer apparatus that transfer multiple dies or an entire die pattern per exposure cannot satisfactorily control aberrations arising in the CPB-optical system through which the charged-particle beam passes, especially over a large optical field covering one or more dies. To solve this problem, CPB pattern-transfer apparatus have been proposed in which a pattern to be transferred is divided into multiple field segments ("mask subfields") that are individually and separately exposed. Such a pattern is typically transferred using a "step-and-repeat" transfer scheme in which the individual mask subfields are sequentially transferred to corresponding "substrate subfields" on a wafer or other sensitized substrate. The substrate subfields are produced on the wafer surface in locations relative to each other such that the substrate subfields are "stitched" together in the correct order and alignment to reproduce the entire die pattern on the wafer surface (e.g., see U.S. Pat. No. 5,260,151).
A demagnifying "reduction" pattern-transfer apparatus irradiates a charged-particle beam onto a portion of a mask defining a circuit pattern of an entire die. An image of the die pattern is then demagnified and formed on the wafer (e.g., see Japanese Laid Open Patent Document No. Hei5-160012). Because a die pattern image cannot be transferred to the wafer with sufficiently high resolution when irradiating the entire die pattern in a single exposure, a step-and-repeat transfer scheme is used to transfer the die pattern to the wafer subfield-by-subfield.
A mask for use with a "partial-batch" pattern-transfer method defines a repeating pattern portion of an integrated circuit, such as a DRAM, and non-repeating patterns. The mask is irradiated and the pattern portion to be repeatedly transferred to the wafer is reduced and transferred thereto the desired number of times. The non-repeating pattern portions of the mask undergo direct writing to the wafer (i.e., the patterns are not reduced), typically using a conventional variable-shaped-beam method. The partial-batch pattern-transfer method improves wafer throughput in comparison to a variable-shaped-beam method.
By providing a mask defining the circuit pattern of an entire integrated-circuit chip and forming a reduced pattern image of the integrated circuit pattern on a sensitive substrate, it is possible to eliminate all need for direct writing of non-repeating pattern portions of a mask. By eliminating direct writing, wafer throughput is increased. However, to provide reduction transfer of all of the die patterns on a mask at a demagnification ratio of 1/20 to 1/50 and ensure the required pattern resolution, the dimensions of the mask pattern must be 20 to 50 times, respectively, the size of the complete wafer integrated-circuit pattern. Accordingly, currently, pattern-transfer demagnification-n ratios are only in the order of 1/2 to 1/4, to avoid having to use a mask having an unreasonable size.
Additionally, masks used for such reduction-pattern-transfer methods typically are made by using a self-supporting, thin film of silicon, having a thickness of about 1 .mu.m to about 30 .mu.m. As masks used for reduction-pattern transfer necessarily increase in size, it is exceedingly difficult to form a self-supporting thin film to form the mask. Additionally, as the mask increases in size, deformations of such thin-film masks increase, making it difficult to ensure accuracy and precision in the formation of mask-pattern images on a wafer.
Moreover, semiconductor wafers for producing a mask of the size required for a higher demagnification ratio are not presently available. For example, for a 15 mm.times.30 mm integrated circuit having a demagnification ratio of about 1/8, the size of the mask-pattern region must be 120 mm.times.240 mm. Accordingly, the diagonal dimensions of the resulting mask would be approximately 268 mm. To produce a mask of such dimensions, a semiconductor wafer having a diameter of about 300 mm would be required; such semiconductor wafers are currently not available commercially.
Further, if a mask is comprised of a self-supporting thin film of silicon rather than comprising a patterned thin film of chrome on a quartz substrate (as is typically used in optical lithographic processes), positional distortion of the mask typically occurs.
The present invention makes it possible to produce a mask having a sufficiently large surface area for reduction-pattern transfer without the need for direct writing, while controlling cost increases in mask production and providing relatively high wafer throughput. In addition to providing the masks of the present invention, the present invention further provides mask-alignment and pattern-transfer methods that substantially eliminate degradation in mask-pattern-transfer accuracy typically associated with use of relatively large masks.